Ldmos transistors for cmos technologies and an associated production method

ABSTRACT

In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region ( 12 ) and the heavily doped feed guiding region ( 28, 28 A), an improved potential profile is achieved in the drain drift region ( 8 ) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.

CROSS-REFERENCE RELATED APPLICATIONS

This application is a Divisional of U.S. patent application Ser. No.13/635,535, filed Dec. 11, 2012, now U.S. Pat. No. 9,224,856, which is aU.S. National Stage Application of International Application ofPCT/IB2011/051505 filed Apr. 7, 2011, which claims benefit of GermanPatent Application No. 10 2010 014 370.7 filed Apr. 9, 2010, thedisclosures of which are herein incorporated by reference in theirentireties.

FIELD OF DISCLOSURE

The invention relates to lateral DMOS transistors (LDMOS) producible inCMOS processes and having improved characteristics and relates to anassociated production method.

BACKGROUND OF THE DISCLOSURE

Power field effect transistors in the form of DMOS transistors(originally: double diffused MOS) have evolved over the last years intoindispensable devices in the semiconductor high-voltage (HV) and powerprocesses. Generally, a field effect transistor comprises so-calleddrain and source regions that are separated by a channel region, whichin turn is controlled by the gate electrode such that a controllablecurrent flow is created between the drain region and the source region.Hereinafter, a power field effect transistor shall be understood as afield effect transistor that is operated at voltages of 15V or higherand/or at drive currents of approximately 500 mA or higher. Hereinafter,field effect transistors are also referred to as MOS transistorsirrespective of the material that is actually used in the gateelectrode.

The active principle of lateral DMOS transistors is based on prolongeddrain regions, across which a part of the voltage to be processed dropsthat, without a voltage drop, would damage the gate area and thereforemust not be applied at the gate electrode at full magnitude. In lateralDMOS transistors (LDMOS) this prolonged area of the drain region,referred to as drain extension or drift region, is arranged parallel tothe surface of the active semiconductor layer of the chip, therebyenabling a simple integration into existing CMOS processes. A CMOSprocess is to be understood as a process strategy, in whichcomplementary field effect transistors, i.e. p-channel transistors andn-channel transistors, are fabricated in and above the activesemiconductor layer. Hence, in the CMOS manufacturing strategy processesare required, which enable the generation of drain and source regions ofp-conductivity and the generation of drain and source regions ofn-conductivity.

To this end, typically appropriate implantation techniques are usedwherein an appropriate masking scheme is employed in order to form thedoped regions with different conductivity type.

Frequently, in such HVCMOS processes, that is in CMOS processes, inwhich field effect transistors are designed for high-power or highvoltage, both n-conductive and p-conductive LDMOS transistors (nLDMOStransistors, pLDMOS transistors) are required. The concurrentoptimisation of both conductivity types at reduced complexity is thus aparticular challenge.

This problem is the subject matter of WO 2008/116880 A1 (X-Fab), which,however, is only insufficiently addressed therein.

The most recent development in DMOS transistors is characterised by theconsequent employment of the RESURF principle (Reduced ElectricalSurface Field), wherein it is increasingly accomplished to resolve thecharacteristic conflict between a breakdown voltage as high as possiblein the off-state (off-breakdown BV_(off)) and low on-resistance(drain-source on-resistance RDSon). A particular class in this respectrepresent the so-called super junction transistors which achieveextraordinarily high conductivity in the drift region at a high BV_(off)by means of nip multi-layers.

With the demand for an increased fraction of digital circuitry in HVCMOSapplications a tendency has evolved towards reduced structuraldimensions of the corresponding basic processes. HVCMOS developmentsnowadays typically take place in 0.35 to 0.13 μm processes, i.e. inprocesses, in which small signal transistors having critical dimensions,such as the gate length, of approximately 200 nm to approximately 65 nmare fabricated, whose field isolation is substantially exclusively basedon shallow trenches including an appropriate insulating fill material(shallow trench isolation STI). The majority of LDMOS transistorsdeveloped in such processes comprises (buried) drift paths extendingbelow the trench isolation region thereby taking advantage of the highquality insulating material of the trench isolation as a top boundary ofthe current path. However, the inclusion of the drift region of suchtransistors at the gate and drain side requires specific constructivemeasures, since the current path has to be guided from the area belowthe trench isolation region back to the surface without compromisingdevice reliability. Furthermore, also in these areas an optimal ratiobetween potential drop and conductivity should prevail.

As a constructive solution for the implementation of the drift region atthe gate side split-gate transistors have been proposed, among others,which allow a manipulation of the electric field near the gate at thebeginning of the drift path independently from the channel field.

For constructing the implementation at the drain side, on the otherhand, the publication WO 2007/103610 A2 (Freescale) proposes to routethe drift path of an LDMOS transistor below the trench isolation regionat the gate side only and to prevent silicidation in the thus prolongedactive region at the drain side by using a silicide blocker.

FIG. 1 illustrates a schematic side view of the conventional power fieldeffect transistor (LDMOS) 150 of this document WO 2007/103610 A2 in theform of an n-channel transistor comprising deeper lying p/n layers thatare referred to as 102, 104 and 106, respectively. That is, the layer102 is n-doped, while the layers 106, 104 are p-doped. Furthermore, inthe lightly p-doped region 106 a p-well 110 is formed, which thusrepresents the p-doped body region of the transistor 100. A heavilyn-doped source region 118 in combination with a heavily p-doped region120 acting as a body connection is formed in the p-well 110.Furthermore, a drain drift region 108 in combination with a heavilydoped drain region 122 is provided, wherein, as discussed above, atrench isolation region 112 is embedded in the drain drift region 108.Moreover, a gate electrode structure 114 comprising a gate dielectric116 is provided above the p-well and a part of the drain drift region108 as well as the trench isolation region 112. The formation ofsilicide on exposed surface areas of the drain drift region 108 isprevented by a dielectric layer 124.

The results of the configuration of the power field effect transistor150 shown in FIG. 1 is a wider current path extending with reducedinclination to the drain region 122, thereby reducing RDS_(on). At thesame time the tendency for impact ionisation (Avalanche) is less due tothe reduced current density. Consequently, for the same drain current areduced bulk current, that is, a current into deeper layers of thetransistor 150, is generated. In this way the turning on of the internalparasitic bipolar transistors (snap-back in the nLDMOS) is delayed,thereby achieving a higher on-breakdown voltage. In particular when—asis typical in cost efficient processes including multiple usage ofmasks—the dopant profile of the drift zone 108 may not exclusively betailored with respect to a single transistor type, with this solutionfrequently BV_(off) is too low due to incomplete depletion in the areaof the drain region 122.

It is an object of the invention to increase the breakdown voltage in asemiconductor device as BV_(off) in LDMOS transistors having a draindrift region, wherein a production of n-conductive and/or p-conductiveLDMOS transistors in the semiconductor device in a CMOS process shouldbe doable as efficiently as possible.

According to one aspect of the present invention this object is solvedby a semiconductor device that comprises a lateral power field effecttransistor. The lateral power field effect transistor comprises a sourceregion of a first conductivity type, a drain region of the firstconductivity type, a drain drift region of the first conductivity type,a trench isolation region that is at least partially embedded in thedrain drift region, and a doped field guiding region of a secondconductivity type that is inverse to the first conductivity type.

In the inventive power field effect transistor the trench isolationregion and in particular the doped field guiding region embedded in thedrain drift region results in a superior electric field distribution,that is, a forced guiding of potential lines is achieved in the vicinityof the drain region, however without pronounced interferences of thefield profile in the lower layers of the semiconductor device takingplace. For example, the RESURF regions remain substantially unaffectedby the field guiding region and also no electrically chargeable zonesare generated. A doped field guiding region or field guide region is tobe understood in this context as an area that is counter-doped withrespect to the drain drift region and thus forms a pn junction therewithand influences the profile of the electrical field within the draindrift region.

To this end in one advantageous embodiment the doped field guidingregion is provided as a region having a freely adjustable potentialwithout an electrical connection. A field guiding region without anelectrical connection is also referred to as floating. In this manner,there is no influence on the field line profile by external voltages.

In advantageous embodiments at least one further field guiding region ofthe second conductivity type is provided in the drain drift region. Inthis manner it is nevertheless possible to achieve a desired control ofthe field profile in the drain drift region on the basis of a basicdopant profile by appropriately selecting the size and/or the number offield guiding regions. In this case in some advantageous embodiments oneof the field guiding regions may directly abut on the trench isolationregion at an edge thereof that faces the drain region. Due to thismeasure a very superior field profile is obtained, since firstly thebottom side of the trench isolation region serves as an efficient meansfor adapting the field profile and thereafter the field guiding regionenables the electrical field in the upper area of the drain drift regionto gradually broaden.

In further advantageous embodiments there is not provided any metalsilicide in a surface of the drain drift region. In this manner theadvantageous field profile that is described in the context of FIG. 1may be improved in that even partially depleted regions in the vicinityof the drain region are avoided, thereby increasing the breakdownvoltage.

In a further advantageous embodiment the lateral power field effecttransistor comprises a doped body connection region of the secondconductivity type adjoining to the source region, wherein the fieldguiding region and the doped body connection region have a same dopantprofile in the depth direction. Therefore these corresponding dopedregions that have an inverse doping type compared to the drain andsource regions may be formed in a common implantation sequence.

In a further advantageous embodiment the maximum dopant concentration ofthe field guiding region is greater than a maximum dopant concentrationof the body connection region. By appropriate selection of the dopantconcentration of the field guiding region in combination with its sizeand also the number of field guiding regions an efficient control of thefield profile in the drain drift region is obtained, while stillstandard implantation processes may be applied. For example, theincreased maximum dopant concentration may be generated by subjectingthe field guiding region in the context of the required implantationprocesses to at least one further implantation process compared to, forinstance, the body connection region.

In a further embodiment the semiconductor device comprises a smallsignal transistor that has deep drain and source regions and shallowdrain and source extension regions. In this context a small signaltransistor is to be understood as a transistor designed for beingoperated at voltages of less than (or equal to) 15V. In this case, thesehighly doped regions of the small signal transistor may havesubstantially the same dopant profiles as the field guiding region,since they are formed during the same implantation sequence. Forexample, the field guiding region may be formed during an implantationfor producing shallow drain and source regions, while in other cases thefield guiding region is produced during the formation of deep drain andsource regions of the small signal transistor, wherein, if required,also the implantation of the shallow drain and source regions may havepreviously been performed in the field guiding region.

In some advantageous embodiments the small signal transistor comprises agate electrode having a gate length of 200 nm (nanometre) or less. Inthis manner the power field effect transistor may be produced on thebasis of a technology, with which also highly sophisticated controltasks may be implemented by providing small signal transistors havingthe above-referenced dimensions.

In further advantageous embodiments there is provided a second lateralpower field effect transistor of complementary conductivity typecompared to the already provided field effect transistor.

According to a further aspect of the claimed dimension theabove-referenced objects is solved by a method for producing asemiconductor device or semiconductor component having a lateral powerfield effect transistor. The method comprises the forming of a trenchisolation region and a drain drift region of a first conductivity typesuch that the trench isolation region is at least partially embedded inthe drain drift region. The method further comprises performing one ormore ion implantation processes for forming deep drain and sourceregions and/or drain and source extension regions in a small signaltransistor of a second conductivity type that is inverse to the firstconductivity type. The method further comprises performing one or morefield guiding regions in the drain drift region by at least one of theone or more ion implantation processes.

In this manner an appropriate field distribution in the drain driftregion of the power transistor is achieved by using implantationprocesses that are also used for forming highly doped regions in smallsignal transistors. Thereby, a highly efficient manufacturing flow isachieved, since no additional process steps are required. To this end,the implantation processes for forming the shallow drain and sourceextension regions and/or the implantation processes for forming the deepdrain and source regions may be used. In particular the implantationprocesses and the associated masking schemes for the formation ofcomplementary small signal transistors may efficiently be used in orderto also form appropriate field guiding regions for complementary powertransistors. To this end appropriate photolithography masks may beproduced, which expose during corresponding surface areas of the draindrift region the respective implantation processes in order to enablethe lateral structure of the field guiding regions to be adjusted in anefficient manner Hence, on the basis of the standard implantationprocesses the desired field profile in the drain drift region mayspecifically be adjusted for the respective application by providingappropriate mask openings without requiring a change of processparameters of the associated implantation processes and without addingfurther process steps.

Generally, the claimed invention enables achievement of higheroff-breakdown voltages at reduced on-resistance and in particular for annLDMOS transistor concurrently higher on-breakdown voltages compared toknown solutions without requiring additional masking steps during theproduction.

Further advantageous embodiments are defined in the dependent claims.

The following detailed description illustrates examples and anexplanation and supplement of the claimed invention. It is to beexpertly studied with reference to the drawings.

FIG. 1 is a sectional illustration of a conventional LDMOS-transistor,as described in WO 2007/103610.

FIG. 2 is a sectional view of a semiconductor device during amanufacturing phase, in which an implantation process for formingshallow drain and source extension regions is performed, wherein, ifrequired, at the same time a field guiding region is formed in a powertransistor.

FIG. 3 as a schematic cross-sectional view of the semiconductor device,wherein an implantation process for forming deep drain and sourceregions is performed.

FIG. 4 is a schematic cross-sectional view of a part of thesemiconductor device after having performed a silicide process.

FIG. 5 is a cross-sectional view of a complementary power field effecttransistor that is provided alternatively or additionally to thetransistor of FIGS. 2 to 4.

FIG. 2 illustrates a schematic cross-sectional view of a semiconductordevice 90 comprising a small signal transistor 50K and a lateral powerfield effect transistor or DMOS transistor 50P. The device 90 comprisesa substrate 30, on which are applied appropriate semiconductor layers,for example epitaxially grown silicon layers. In the embodiment shownthere is provided a lightly n-doped layer 4 that serves as a body regionof the transistor 50P, thus representing a p-channel transistor. On theother hand there is formed in the layer 4 a p-doped body region or bulkregion 10 of the transistor 50K that is therefore an n-channeltransistor. The lateral size of the small signal transistor 50K isdetermined by respective trench isolation regions 12. A correspondingtrench isolation region 12 is also provided in a drain drift region 8 inorder to obtain a superior potential profile, as is already explained inthe context of the transistor 150 of FIG. 1. The drain drift region 8 istherefore a corresponding p-doped region in which a heavily doped drainregion is to be formed in further manufacturing processes.

In the manufacturing stage shown the transistors 50K and 50P comprisegate electrode structures 14K and 14, respectively, which compriseisolation layers 16K and 16, respectively. Furthermore, an implantationmask 26 is provided that exposes the transistor 50K in order to formshallow n-doped drain and source extension regions 23 in the body region10. In the embodiment shown the implantation mask 26, which may beprovided in the form of a resist mask, for instance, includes anappropriate opening 27 such that a field guiding region 28E is producedin the drain drift region 8, wherein the lateral size and position ofthe region 28E in the drain drift region 8 are determined by the maskopening 27. For example, the lateral dimension 27L of the opening 27 maybe adjusted as is demonstrated by the dashed line in order to generatean appropriate field guiding or bending, respectively, of potentiallines depending on the dopant profile that is obtained by animplantation process 25. The implantation process 25 is thus performedas a standard implantation process as required for forming the region 23in the transistor 50K. The appropriate adaptation of the field guidingbehaviour of the region 28E is thus accomplished by constructivemeasures, i.e. the formation of the implantation mask 26 including theopening 27.

The semiconductor device 90, as shown in FIG. 2, may thus be formed onthe basis of standard CMOS processes. That is, prior to or after theformation of the trench isolation regions 12 based on well knowntechniques, if required, the implantation processes for deeper lyingareas of the device 90 are performed, for example for the drain driftregion 8 and the body region 10, by applying appropriate maskingstrategies, followed by processes for forming the gate electrodestructures 14K and 14, respectively. To this end, process technologiesmay be used with which the gate electrode structure 14K having a gatelength of 200 nm or less is patterned. Thereafter the mask 26 is formedby appropriate lithography processes.

FIG. 3 illustrates the semiconductor device 90 in a further advancedmanufacturing phase, in which a further implantation process 29 isperformed on the basis of a mask 30. During the implantation process 29there are formed in the transistor 50K deep drain and source regions 32that, in combination with the region 23, result in the desired dopantprofile for the transistor 50K after performing corresponding annealprocesses.

In the embodiment illustrated the mask 30 includes an opening 31 thatdefines the lateral position and size and hence the shape of a fieldguiding region 28 that is produced by the implantation process 29 in thedrain drift region 8. The regions 32 and 28 thus have a substantiallyidentical dopant profile in a depth direction T that is to be understoodas the vertical direction in FIG. 3. In the embodiment illustrated theentire vertical dopant profile is also determined by the region 28E dueto the already previously introduced dopants for forming the region 28E,while in other embodiments (not shown) the dopant profile of the region28 is exclusively formed by the implantation 29 or exclusively by theimplantation 25 of FIG. 2, that is, in the form of the region 28E.Moreover, the implantation 29 and the formation of the mask 30 areperformed on the basis of standard process technologies. As shown inillustrative embodiments also a mask opening 33 may be provided, when aheavily n-doped body or bulk connection region 20 is additionally to beformed during the standard implantation process 29. If required acorresponding opening may also be provided during the implantationprocess 25 of FIG. 2, if an increased dopant concentration at least atthe surface is desired, as is the case for the combination of theregions 23 and 32. Thus, when identical implantation conditions areapplied for the regions 20 and 28, these regions have substantiallyidentical dopant profiles along the depth direction T.

FIG. 4 illustrates the semiconductor device 90 in a further advancedmanufacturing phase, in which, for simplicity, only the transistor 50Pis shown. In the manufacturing phase shown a heavily doped source region18 and the corresponding inversely and heavily doped body connectionregion 20 are provided, while a heavily doped drain region 22 is formedin the p-doped drain drift region 8. Moreover, one or more field guidingregions 28 and 28A, respectively, are provided in an area of the driftregion 8 with appropriate lateral position, size and shape in order toachieve the desired potential line profile in the drift region 8, as isalso explained above. Corresponding metal silicide materials 18S, 20S,22S, 28S are formed on the surface of the heavily doped drain region 18,the heavily doped body connection region 20, the heavily doped sourceregion 22 and, in the embodiment shown, the heavily doped field guidingregion 28. Moreover, a metal silicide 14S is also present in the gateelectrode structure 14. Furthermore, surface areas of the drift region8, on which no metal silicide is to be formed, are covered by a silicideblocking mask 24.

The semiconductor device 90 shown in FIG. 4 may be formed on the basisof standard CMOS processes, wherein in particular the heavily dopeddrain and source regions 18, 22 may be formed in the context ofimplantation processes for p-type small signal transistors, as isrepresentatively shown for example for then-channel transistor 50K inFIGS. 2, 3 with respect to the formation of the regions 28, 28A and 20that are inversely doped with respect to the drain and source regions22, 18. That is, the regions 18 and 22 are formed by standardimplantation processes for p-channel transistors while covering theremaining surface of the region 8, whereas the heavily doped fieldguiding region or regions 28 and 28A, respectively, as well as theheavily doped body connection region 20 are produced during one or morecorresponding implantation processes, in which the heavily doped drainand source regions of n-channel transistors are formed. In embodiments,in which the regions 20 and 28 or 28A have been formed under identicalprocess conditions, these regions have substantially identical dopantprofiles in the depth direction, that is, in FIG. 4 the verticaldirection. After the generation of the corresponding dopant profilesappropriate anneal techniques are performed in order to adjust the finallateral and vertical profile of these doped regions. Thereafter, thesilicide blocking mask 24 may be formed by standard depositiontechniques, lithography processes and patterning techniques. To thisend, materials such as silicon dioxide, silicon nitride and the like areappropriate. Thereafter, metal silicide is formed, for instance byapplying an appropriate refractory metal and causing reaction thereofwith the silicon on in the exposed semiconductor surfaces. After theremoval of excess metal the structure shown in FIG. 4 is obtained.

FIG. 5 schematically illustrates the semiconductor device 90, wherein atransistor 50N is provided, which is produced additionally oralternatively with respect to the transistor 50P (cf. FIGS. 2 to 4). Thetransistor 50N is an n-channel transistor and is thus a transistorcomplementary to the transistor 50P. In this case the drift region 8 isan n-doped region, while the body region 4 is a p-doped region.Analogously, the heavily doped drain and source regions 18, 22 areheavily n-doped regions, while the body connection region 20 is aheavily p-doped region. Accordingly, the heavily doped field guidingregion 28 is a p-doped region.

The transistor 50N may also be formed on the basis of standard CMOSprocesses, wherein during the implantation of drain and source regionsand/or extension regions of small signal transistors of p-conductivitythe one or more regions 28 may be formed partly or completely togetherwith the region 20. Similar processes may be applied, as are previouslyexplained for the transistor 50P, wherein, however, the dopant types tobe introduced during the corresponding implantation processes are to bereversed.

The LDMOS transistors 50P, 50N shown in FIGS. 2 to 4 on the one hand andin FIG. 5 on the other hand are different from each other with respectto the type of conductivity and with respect to the fact that in thepLDMOS 50P the implantation region 8 forming the drift area or pathterminates below the gate 14. In the nLDMOS 50N the drift path consistsof the corresponding part of the n-well 8 and the body region 4 isformed in the drift region 8 as a well. Both LDMOS transistors havedrift paths extending partially below the STI region 12, wherein in onepreferred embodiment a field guiding region 28 is disposed on the STIedge 12A facing the drain region 22 such that an appropriate fieldprofile is obtained towards the surface and towards the drain region 22.

By using the same methods, i.e. also identical mask levels for thetransistors 50K, 50P, 50N a cost efficient and reliable production isachieved. In one embodiment only implantation steps present in thestandard CMOS processes for source and drain regions are used for thehighly doped regions 28, 28A such that no additional masking steps arerequired. In this case, the inventive floating regions 28, 28A guaranteean appropriate field guiding, that is, a forced guiding of the potentiallines (bending) in the vicinity of the drain region 22 withoutdisturbing the RESURF balance in the depth or creating electricallychargeable zones. Of particular advantage is the adjustability of thetarget geometry and/or target concentration of the inventive floatingregions 28, 28A by co-operation of STI edge 12A and implantation masks,for example the masks 26 and 30.

LIST OF REFERENCE SIGNS (EXCERPT)

-   -   102 n-layer    -   104, 106 p-layer    -   108 n-doped drift area (extended drain)    -   110 p-doped region (bulk or body)    -   112 trench isolation region (STI)    -   114 gate electrode    -   116 gate insulator    -   118 n+ source    -   120 p+-bulk connection or body region connection    -   122 n+-drain    -   124 dielectric insulation layer (silicide blocker)    -   150 n-LDMOS transistor    -   4 body region or bulk region    -   8 p or n-drift region    -   12 STI    -   14, 14K gate    -   16, 16K gate insulation layer    -   18 source    -   20 bulk or body connection    -   22 drain    -   23 drain and source extension region    -   24 silicide blocker    -   25 extension implantation for shallow drain and source extension        regions (LDD implantation)    -   26 resist mask    -   27 mask opening    -   27L lateral dimension of the mask opening    -   28, 28A highly doped region of opposite conductivity type with        respect to source and drain    -   29 deep drain and source implantation    -   30 resist mask    -   31 mask opening    -   32 deep drain and source regions    -   33 mask opening    -   50K small signal transistor (voltage range<=15V)    -   50P p-channel power transistor (voltage range above 15V)    -   50N n-channel power transistor (voltage range above 15V)    -   90 semiconductor device

We claim:
 1. A semiconductor device comprising: a lateral power fieldeffect transistor having a source region of a first conductivity type; adrain region of the first conductivity type; a drain drift region of thefirst conductivity type and having a surface; a trench isolation regionthat is at least partially embedded in the drain drift region; and adoped field guiding region of a second conductivity type; wherein thesecond conductivity type is the inverse of the conductivity type.
 2. Thesemiconductor device of claim 1, wherein the doped field guiding regionis provided as a region having a freely adjustable potential without anelectrical connection.
 3. The semiconductor device of claim 1, whereinat least one further field guiding region of the second conductivitytype is provided in the drain drift region.
 4. The semiconductor deviceof any of claim 1, wherein the doped field guiding region is directlyadjacent to the trench isolation region at an edge that faces the drainregion.
 5. The semiconductor device of claim 1, wherein a surface of thedrain drift region is provided with a layer for preventing the formationof silicide.
 6. The semiconductor device of claim 1, wherein the lateralpower field effect transistor further comprises a doped body connectionregion of the second conductivity type directly adjacent to the sourceregion.
 7. The semiconductor device of claim 6, wherein the doped bodyconnection region and the doped field guiding region have a same dopantprofile in a depth direction thereof.
 8. The semiconductor device ofclaim 6, wherein a maximum dopant concentration of the doped fieldguiding region is greater than a maximum dopant concentration of thedoped body connection region.
 9. The semiconductor device of claim 1,further comprising a small signal transistor that comprises a deep drainand a source region and a shallow drain and a source extension region ofthe second conductivity type.
 10. The semiconductor device of claim 9,wherein the deep drain and source extension region and the doped fieldguiding region have a same dopant profile in a depth direction thereof.11. The semiconductor device of claim 9, wherein the deep drain andsource regions and the doped field guiding region have a same dopantprofile in a depth direction thereof.
 12. The semiconductor device ofclaim 9, wherein the small signal transistor comprises a gate electrodehaving a gate length of 200 nm or less.
 13. The semiconductor device ofclaim 1, further comprising: a second lateral power field effecttransistor having a second source region of the second conductivitytype, a second drain region of the second conductivity type, a seconddrain drift region of the second conductivity type, a second trenchisolation region at least partially embedded in the second drain driftregion, and at least one second doped field guiding region of the firstconductivity type.